Detailed Analysis of the Fetch-Decode-Execute Cycle and Register Logic Operation

Program Counter (PC): A dedicated register that holds the memory address of the next instruction to be fetched. It keeps track of the program's progress through memory.
Memory Address Register (MAR): A register that holds the memory address currently being accessed for either reading (fetching an instruction or data) or writing (storing data).
Memory Data Register (MDR): A temporary storage buffer that holds the data or instruction fetched from memory, or the data waiting to be written to memory.
Current Instruction Register (CIR): A register that holds the current instruction while it is being decoded and executed. It splits the instruction into its opcode (instruction type) and operand (data or address).
Accumulator (ACC): A primary register in the Arithmetic Logic Unit (ALU) used to store the results of mathematical and logical operations.
Address Bus: A unidirectional communication pathway used by the CPU to send the specific address it wants to access in memory.
Data Bus: A bidirectional communication pathway used to transport the actual data or instructions between the CPU and memory.
Control Bus: Carries control signals (such as Read or Write) from the CPU to other components to coordinate operations.

The program and data are stored in memory at the following specific addresses: - Address $1$ : Contains the instruction LOAD 5. - Address $2$ : Contains the instruction ADD 6. - Address $3$ : Contains the instruction STO 7. - Address $4$ : Empty/Not specified. - Address $5$ : Contains the data value $8$ . - Address $6$ : Contains the data value $4$ . - Address $7$ : Initially empty (reserved for output).

Fetch Stage: - The PC contains the address $1$ . - The value $1$ is copied from the PC to the MAR via the Address Bus. - The CPU sends a read signal to memory. The instruction at address $1$ (LOAD 5) is transferred via the Data Bus to the MDR. - The PC is incremented from $1$ to $2$ to prepare for the next cycle. - The instruction LOAD 5 is copied from the MDR to the CIR.
Decode Stage: - The CIR decodes the instruction LOAD 5. The CPU identifies the opcode LOAD (meaning fetch data from a memory address and place it in the Accumulator) and the operand address $5$ .
Execute Stage: - The operand address $5$ is moved to the MAR. - The value at address $5$ ( $8$ ) is fetched from memory via the Data Bus and placed into the MDR. - The value $8$ in the MDR is then copied into the Accumulator (ACC). - Current State: ACC = $8$ .

Fetch Stage: - The PC contains the address $2$ . - The value $2$ is copied from the PC to the MAR. - The instruction at memory address $2$ (ADD 6) is fetched and sent via the Data Bus to the MDR. - The PC is incremented from $2$ to $3$ . - The instruction ADD 6 is copied from the MDR to the CIR.
Decode Stage: - The CIR decodes the instruction ADD 6. The CPU identifies the opcode ADD (meaning add the value at a specified memory address to the current value in the Accumulator).
Execute Stage: - The operand address $6$ is moved to the MAR. - The value at address $6$ ( $4$ ) is fetched via the Data Bus and placed into the MDR. - The ALU performs the addition: Current ACC value ( $8$ ) plus MDR value ( $4$ ). - The result, $12$ , is stored back in the Accumulator (ACC). - Current State: ACC = $12$ .

Fetch Stage: - The PC contains the address $3$ . - The value $3$ is copied from the PC to the MAR. - The instruction at memory address $3$ (STO 7) is fetched and sent via the Data Bus to the MDR. - The PC is incremented from $3$ to $4$ . - The instruction STO 7 is copied from the MDR to the CIR.
Decode Stage: - The CIR decodes the instruction STO 7. The CPU identifies the opcode STO (meaning store the value currently in the Accumulator into a specified memory address).
Execute Stage: - The operand address $7$ is moved to the MAR. - The value in the Accumulator (ACC), which is $12$ , is copied to the MDR. - The CPU sends a write signal, and the value $12$ in the MDR is transferred via the Data Bus to memory address $7$ . - Final State: Memory Address $7$ now contains the value $12$ .