Optimization/Hardware

  1. While←> do-until

    1. If possible use do-until; saves one branch instruction

  2. Variables: put variables in registers if possible

  3. For-Loop

    1. If possible, count down to 0; saves compare instruction


Pipelining

  • To fetch and executed instruction, several operations have to be performed sequentially:

    • 1. Fetch, 2. Load data, 3. Manipulate data, 4. Store data

  • Instruction fetch/execute over time without pipeline.


I1        I2        I3        I4

FLMS,FLMS,FLMS,FLMS

10 instructions, this will take 40 clock ticks


  • Instruction Fetch/execute with 4-stage pipeline

I1    FLMS

I2      FLMS

I3        FLMS

I4         FLMS


10 instructions, 13 clock ticks

Cannot build this pipeline because it’s trying to read and write to memory at the same time. Using Von Neumann

Have to use Harvard architecture to fetch instruction and data at the same time. However, we still have to load and store data at the same time.


Double Data Rate (DDR) is able to first store the data item, then load the data item in one clock tick, doubling the data rate.

Harvard architecture is running on processor chip. Computers use both Von Neumann and Harvard together.


Problems when Branching or Looping because you are fetching the next instruction before you compute to branch. The compiler rearranges the instructions. You can also add a NULL (NOP) instruction. The compiler can also stall the pipeline for 1 clock tick by not usign the fetch engine for 1 tick.


Pipeline Problems

  • Jumping/branching in program

    • Incorrect instructions already in pipeline

    • Processor has to stall pipeline (temporary loss of performance)

    • Dynamic branch prediction during runtime

  • Data Dependencies

    • Intelligent compiler rearranges instructions

    • Dynamic instruction scheduling during runtime

    • Data forwarding in pipeline during runtime

Multiple ALU


Flynn’s computer architecture Taxonomy

  • SISD

    • Single instruction Stream

    • Single data stream

    • E.g., Uniprocessor

  • MISD

    • Multiple instruction streams

    • single data stream

    • not used

  • SIMD

    • Single instruction Stream

    • Multiple data streams

    • e.g., VEctor processors, GPUs, MMX - Multi Media Extension

  • MIMD

    • Multiple instruction streams

    • multiple data streams

    • e.g., Multicores, clusters, server farms