Computer Organization: Input/Output, Instruction Sets, and Processor Design

Evolution of the I/O Function

The development of Input/Output functionality in computer systems has evolved through several distinct stages, moving from direct CPU control to autonomous I/O processors.

• Step 1: Direct CPU Control

  • The Central Processing Unit (CPU) directly manages and controls a peripheral device.

• Step 2: Addition of a Controller/I/O Module

  • A dedicated controller or I/O module is introduced to the architecture.

  • The CPU utilizes programmed I/O without the use of interrupts.

  • The CPU must wait for the I/O operation to complete, which is inefficient.

• Step 3: Introduction of Interrupts

  • Utilizes the same configuration as Step 2 but incorporates interrupts.

  • The CPU no longer needs to wait for an I/O operation to be performed; it can proceed with other tasks until the I/O module signals completion via an interrupt, increasing overall system efficiency.

• Step 4: Direct Memory Access (DMA)

  • The I/O module is granted direct access to memory through a DMA controller.

  • It can move a block of data directly to or from memory without CPU involvement, except for the initial setup and the final notification of completion.

• Step 5: Specialized I/O Processors

  • The I/O module is enhanced to become a processor in its own right.

  • It features a specialized instruction set specifically tailored for I/O operations.

• Step 6: Autonomous I/O Computers

  • The I/O module possesses its own local memory and acts as a computer in its own right.

  • This architecture allows a large set of I/O devices to be controlled with minimal CPU involvement.

I/O Channel Architecture

I/O channels represent an extension of the DMA concept, acting as interfaces or pathways to transfer data between devices (e.g., hard drives, printers) and memory.

• Capabilities and Control

  • An I/O channel can execute its own I/O instructions, giving it complete control over I/O operations.

  • In systems with these devices, the CPU does not execute I/O instructions; instead, these instructions are stored in main memory to be executed by a special-purpose processor in the I/O channel called an I/O Controller.

  • I/O Processor vs. I/O Controller: While I/O channels execute their own instructions, they are not designed for complex data processing. I/O processors are the units that handle more complicated data manipulation tasks.

• CPU Initiation and Program Specification

  • The CPU initiates a transfer by instructing the I/O channel to execute a program in main memory.

  • The program specifies:

    • The target device or devices.

    • Memory areas for storage.

    • Priority levels.

    • Required actions for specific error conditions.

• Types of I/O Channels

  • Selector Channel: Controls multiple high-speed devices. At any one time, it is dedicated to transferring data with exactly one of those devices. Each device (or small set) is handled by a controller/I/O module; the selector channel acts in place of the CPU to control these controllers.

  • Multiplexor Channel: Handles I/O with multiple devices simultaneously.

    • Byte Multiplexor: Used for low-speed devices. It accepts or transmits characters to multiple devices. For example, character streams from three devices ($A_1A_2A_3...$, $B_1B_2B_3...$, $C_1C_2C_3...$) might be interleaved as $A_1B_1C_1A_2C_2A_3B_2C_3A_4$.

    • Block Multiplexor: Used for high-speed devices. It interleaves entire blocks of data from several different devices.

Parallel and Serial I/O

The interface to a peripheral must be tailored to its operation. A major characteristic is whether the connection is serial or parallel.

• Parallel Interface

  • Features multiple lines connecting the I/O module and the peripheral.

  • Multiple bits are transferred simultaneously, similar to bits of a word moving over a data bus.

  • Traditionally used for high-speed peripherals like tape and disk drives.

• Serial Interface

  • Uses only one line to transmit data.

  • Bits must be transmitted one at a time.

  • Traditionally used for printers and terminals.

  • Modern Trend: With the emergence of high-speed serial interfaces, parallel interfaces are becoming less common.

External Interface Configurations

• Point-to-Point Configuration

  • Provides a dedicated line between the I/O module and the external device.

  • Typical in small systems (PCs, workstations) for keyboards, printers, and external modems.

  • Example: EIA-232 specification.

• Multipoint Configuration

  • Used to support external mass storage (disk, tape) and multimedia devices (CD-ROMs, video, audio).

  • These are essentially external buses.

Peripheral Connection Technologies

• Thunderbolt

  • Developed by Intel in collaboration with Apple.

  • Combines data, video, audio, and power into one high-speed connection.

  • Throughput: Up to $10\,Gbps$ in each direction.

  • Power: Provides up to $10\,Watts$ to connected peripherals.

  • More complex than simple USB devices; aimed at professional consumers/audiovisual editors.

• InfiniBand

  • Aimed at high-end servers, released in 2001.

  • Standard for data flow among processors and intelligent I/O devices.

  • Switch-Based Architecture: Can connect up to $64,000$ servers, storage systems, and networking devices.

  • Virtual Lanes: Each physical link supports up to $16$ logical channels. One lane is reserved for fabric management; others are for data transport.

  • Protocol Layers: Physical, Link, Network, and Transport.

  • Effective Throughput (Send + Receive):

    • 1-wide link: Signal rate $2.5\,Gbps$; Effective throughput $250 + 250\,MBps$.

    • 4-wide link: Signal rate $10\,Gbps$; Effective throughput $1 + 1\,GBps$.

    • 12-wide link: Signal rate $30\,Gbps$; Effective throughput $3 + 3\,GBps$.

IBM zEnterprise 196 (Case Study)

• Mainframe introduced in 2010 based on the z196 chip ($5.2\,GHz$ multi-core with $4$ cores per chip).

• Can have up to $24$ chips ($96$ cores).

• I/O Subsystem: Up to $4$ of the $96$ cores can be dedicated to I/O, creating $4$ Channel Subsystems (CSS).

• CSS Elements: System Assist Processor (SAP), Hardware System Area (HSA), Logical Partitions, Subchannels, Channel Path, and Channel.

Machine Instruction Characteristics

Processor operation is determined by the machine instructions it executes, collectively known as the instruction set.

• Instruction Elements

  • Operation Code (Opcode): A binary code specifying the operation to be performed.

  • Source Operand Reference: Inputs for the operation.

  • Result Operand Reference: Where the output is produced.

  • Next Instruction Reference: Specifies where the processor should fetch the next instruction.

• Operand Locations

  • Main or Virtual Memory: Address must be supplied.

  • I/O Device: Instruction specifies the I/O module and device. If memory-mapped I/O is used, it is treated as a memory address.

  • Processor Register: Instruction contains the unique number/name of the register.

  • Immediate: The operand value is contained directly in a field within the instruction.

• Instruction Cycle State Diagram

  1. Instruction Address Calculation

  2. Instruction Fetch

  3. Instruction Operation Decoding

  4. Operand Address Calculation

  5. Operand Fetch

  6. Data Operation

  7. Operand Store (with potential return for string or vector data)

Instruction Types and Addresses

• Functional Categories

  • Data Processing: Arithmetic and Logic (Boolean) instructions.

  • Data Storage: Movement into/out of registers and memory.

  • Data Movement: I/O instructions for users and external data transfer.

  • Control: Test instructions (status checks) and Branch instructions (decision making).

• Number of Addresses per Instruction

  • 3 Addresses: $OP\,A, B, C \Rightarrow A \leftarrow B\,OP\,C$

  • 2 Addresses: $OP\,A, B \Rightarrow A \leftarrow A\,OP\,B$

  • 1 Address: $OP\,A \Rightarrow AC \leftarrow AC\,OP\,A$ (uses an Accumulator).

  • 0 Address: $OP \Rightarrow T \leftarrow (T-1)\,OP\,T$ (uses a Stack).

• Trade-offs in Address Count

  • Fewer Addresses: Results in more primitive/shorter instructions and less complex processors. However, programs are longer (more total instructions) and have longer total execution times.

  • More Addresses: Results in less primitive/longer instructions and more complex processors. Programs require fewer total instructions.

  • Modern standard: A mixture of two- and three-address instructions is commonly used for flexibility.

Data Types and Operand Types

• Numbers

  • Limited by magnitude representable and precision (for floating-point).

  • Common types: Binary integer (fixed point), Binary floating point, and Decimal.

• Characters

  • IRA (International Reference Alphabet): Known as ASCII in the US.

  • EBCDIC (Extended Binary Coded Decimal Interchange Code): Used primarily on IBM mainframes.

• Logical Data

  • An $n$-bit unit consisting of $n$ 1-bit items ($0$ or $1$).

  • Advantages: Efficient memory usage (Boolean arrays) and bit-level manipulation (useful for software floating-point or code conversion).

• x86 Data Types (Table 12.2)

  • General: Byte, word ($16$ bits), doubleword ($32$ bits), quadword ($64$ bits), double quadword ($128$ bits).

  • Integer: Signed (two's complement) or Ordinal (unsigned).

  • BCD: Unpacked (one digit per byte) or Packed (two digits per byte).

  • Pointers: Near (offset within segment) or Far (segment selector + offset).

  • Strings: Bit field, Bit string (up to $2^{32}-1$ bits), and Byte string.

Instruction Operations and Logic

• Common Processor Actions

  • Data Transfer: Specify source/destination, data length, and addressing mode.

  • Arithmetic: Add, Subtract, Multiply, Divide (for fixed-point, floating-point, or packed decimal). Single-operand instructions include Absolute, Negate, Increment ($+1$), and Decrement ($-1$).

  • Logical Operations: NOT, AND, OR, XOR, and Equivalence (P=Q).

  • Shift and Rotate (Table 12.7 Example with $10100110$):

    • Logical Right Shift (3 bits): $00010100$

    • Logical Left Shift (3 bits): $00110000$

    • Arithmetic Right Shift (3 bits): $11110100$ (preserves sign bit)

    • Arithmetic Left Shift (3 bits): $10110000$

    • Right Rotate (3 bits): $11010100$

    • Left Rotate (3 bits): $00110101$

  • Conversion: Example includes decimal to binary or IBM’s Translate (TR) instruction (8-bit code conversion).

  • System Control: Privileged instructions reserved for the OS (e.g., modifying storage protection keys or control registers).

• Transfer of Control

  • Branch: Conditional (e.g., BRZ - Branch if Zero) or Unconditional.

  • Skip: Implied address (usually skips the next instruction). Example: Increment-and-skip-if-zero (ISZ).

  • Procedure Call: Involves a CALL (branch to procedure) and RETURN (return to original point). Used for economy (code reuse) and modularity. Nested procedures are typically implemented using a stack to store return addresses.

Instruction Formats and Addressing Modes

• Instruction Format Design

  • Defines bit layout and fields (Opcode, Addressing mode).

  • Affected by memory size, bus structure, and processor complexity.

  • Variable-Length Instructions: Efficient and compact but increase processor complexity as the processor doesn't know the exact length of the next instruction in advance.

• Common Addressing Modes (EA = Effective Address)

  • Immediate: Operand = A. Fast (no memory ref), but limited magnitude ($MOV\,CL,\,\#03h$).

  • Direct: EA = A. Simple, but limited address space ($MOV\,CX,\,1234h$).

  • Indirect: EA = (A). Large address space ($2^N$ for word length $N$), but requires multiple memory references ($MOV\,CX,\,[1234h]$).

  • Register: EA = R. Fast (no memory ref), but limited registers ($MOV\,AX,BX$).

  • Register Indirect: EA = (R). Large address space, uses one less memory reference than standard indirect ($MOV\,AX,\,[SI]$).

  • Displacement: EA = A + (R). Combines direct and register indirect. Types:

    • Relative Addressing: EA is displacement from Program Counter (PC).

    • Base-Register Addressing: Register holds base address; instruction holds displacement (useful for segmentation).

    • Indexed Addressing: Address field is memory address; register holds displacement (useful for iterative operations).

  • Stack: EA = top of stack. Implied addressing using a stack pointer.

Processor Organization

• Basic Processor Requirements

  1. Fetch Instruction: Read from memory/cache.

  2. Interpret Instruction: Decode the action.

  3. Fetch Data: Read from memory/IO.

  4. Process Data: Perform arithmetic/logic.

  5. Write Data: Write results to memory/IO.

• Internal Structure

  • Control Unit: Decodes instructions and manages data flow.

  • ALU (Arithmetic and Logic Unit): Contains status flags, shifter, complementer, and boolean logic circuits.

  • Registers: Small internal memory for temporary storage. Divided into:

    • User-Visible Registers: For programmers to minimize memory references.

    • Control and Status Registers: Used by the control unit to manage processor operation and by the OS for execution control.