Electronics Circuits and Systems II — Quick-Review Notes

Demultiplexer vs. Decoder

• Demultiplexer (Demux): single data input, $n$ control lines, $2^n$ mutually-exclusive outputs; routes the single input to one selected output.
• Decoder: $n$ data inputs, $2^n$ outputs; converts binary code to one-hot code (no data input to route).
• Block symbols: Demux – triangle with $1$ input, multiple outputs. Decoder – block with $n$ inputs on left, $2^n$ outputs on right.

Using a $4!:!16$ Decoder to Realise Logic Functions

• Generate $16$ minterm lines $D<em>0 \ldots D</em>{15}$.
• Form each function by OR-ing required minterms:
– $F<em>1(A,B,C,D)=\Sigma(0,1,2,4,6,7,12,14)$ – $F</em>2(A,B,C,D)=\Sigma(3,5,8,10,13,15)$
– $F_3(A,B,C,D)=\Sigma(5,6,7,11,12)$
• OR gates may share minterm lines for economy.

Railway-Platform Priority Decoder (Concept)

• Inputs: platform busy switches $P<em>1,P</em>2,P<em>3,P</em>4$ (logic $1$ when OCCUPIED).
• Outputs: track-changer controls $T<em>1,T</em>2,T<em>3$ and outer signal $S$. • Design rules: – Give highest priority to lowest-numbered free platform. – $S=1$ (green) iff at least one platform free. • Implement with combinational priority logic using AND/OR/NOT only (no storage): – Free flags $F</em>i=\overline{P<em>i}$. – Select $P</em>1$ when $F<em>1$; else $P</em>2$ when $\overline{F<em>1}F</em>2$; etc.
– Derive $T<em>1,T</em>2,T_3$ from selected path truth table.

RAM Technologies

• Bipolar RAM: Schottky TTL cells; very fast access (≈$10$ ns) but high power & low density.
• MOS RAM: NMOS/CMOS; lower power, higher density, slower (≈$45$ ns+).
• DRAM cell vs. SRAM cell:
– DRAM: single MOS + capacitor ⇒ refresh, very high density, low cost, slower.
– SRAM: $6$-MOS latch ⇒ no refresh, faster, lower density, higher power per bit.

Fundamental Memory Terms

• Memory Address Register (MAR): holds address of word to access; size = address bits.
• Memory Buffer Register (MBR): data register (read/write) whose width = word length.
• Memory Cycle Time: minimum time between successive independent accesses (includes access + recovery).
• Volatile Memory: retains data only while power applied (e.g.
DRAM, SRAM).

Example – $8\text{K}\times20$ Memory

• Words stored: $8\,192$.
• Bits stored: $8\,192\times20=163\,840$.
• Address bits: $\log_2 8\,192 = 13$ ⇒ $\text{MAR}=13$ bits.
• $\text{MBR}=20$ bits (word size).

Expanding $16\times4$ (7489) to $16\times8$

• Parallel connect two identical ICs.
• Tie address lines $A<em>0$–$A</em>3$ and enable pins together.
• Lower-order chip supplies data bits $D<em>0$–$D</em>3$, upper chip $D<em>4$–$D</em>7$.
• Outputs form an $8$-bit word per address.

D/A Converter Essentials

• Key specs: resolution (LSB), accuracy, monotonicity, differential/integral linearity, settling time, output drive.
• Bits for $10$ mV resolution on $10$ V full scale:
$N=\lceil \log<em>2(10/0.01) \rceil =10$ bits. • $12$-bit converter, $V</em>{FS}=10$ V ⇒ $\text{LSB}=\dfrac{10}{2^{12}-1}=2.44\text{ mV}$; percentage $=0.0244\%$.

$5$-bit Ladder DAC (input $0$=$0$ V, $1$=$10$ V)

• Contribution of bit $k$ (MSB $k=4$) $=10\text{ V}/2^{5}\times2^{k}$.
• Output for $10110$ $=10\times(1/2+0/4+1/8+1/16+0/32)=10\times0.8125=8.125\text{ V}$.
• Full-scale (all $1$): $10\times(1-1/32)=9.6875\text{ V}$.

Counter-(Ramp) Type ADC

• Blocks: sample-and-hold, binary counter, DAC, comparator, clock.
• Operation: counter runs until DAC ≥ $V<em>{IN}$ → comparator stops count; counter value = digital output. • Example (given): – $\text{LSB}=20.46/1023=0.02\text{ V}$. – Digital code for $V</em>A=7.456$ V ⇒ $\lfloor7.456/0.02\rfloor=372<em>{10}=101110100</em>{2}$.
– Conversion time: $372$ counts / $2\text{ MHz}=186\text{ µs}$.
– Resolution $=0.02\text{ V}$.

Programmable Logic Devices (PLDs)

• Families: PROM, PLA, PAL, GAL, CPLD, FPGA.
• PLA: both AND & OR planes programmable; allows any sum-of-products; outputs may be registered.
• Example PLA ($3$ inputs, $4$ product terms, $2$ outputs) realises $F<em>1$, $F</em>2$ from specified minterms.

TTL NAND (Totem-Pole) Gate

• Multi-emitter input transistor → phase-splitter → totem-pole output pair provides low-impedance pull-up/pull-down.
• Pros: high speed, good fan-out, symmetrical transitions.
• Cons: higher power, requires careful bus wiring (no wired-OR).

Bus-Oriented Logic Gates

• Tri-state buffer & inverter are basic bus drivers; output can be $0$, $1$, or high-Z (disconnect) enabling shared lines.

Bistable Devices

• Clocked RS FF waveforms: level-sensitive; ignore simultaneous $R=S=1$.
• NAND gate latch with cross-feedback behaves as RS FF – truth table verifies.
• JK FF eliminates invalid state; master-slave arrangement (two cascaded latches) achieves edge-triggering.

Ring vs. Johnson Counters

• Ring: $n$ FFs circulate a single $1$ ⇒ $n$ distinct states.
• Johnson (twisted ring): complement of last FF fed to first ⇒ $2n$ states; pattern for $4$-bit: $0000,1000,1100,1110,1111,0111,0011,0001$ then repeats.

Counter Designs

• Divide-by-$10$ asynchronous (ripple) using T-FFs: connect four FFs for binary count, decode $1010$ with gate → asynchronous clear.
• Synchronous Mod-$10$ with non-binary sequence $0,2,4,5,6,8,9,3,1,7$:
– Draw state diagram (arrows follow sequence).
– Transition table lists present / next states & required JK inputs.
– Karnaugh maps give minimal expressions.
– Implement with $4$ JK FFs plus gating for next-state logic.