Combinational Logic Gates and Switching Theory Study Guide

Overview of Combinational and Sequential Logic

• Definition of Logic: Development of a logical conclusion based on known information.

• Combinational Logic:

  • Refers to logic where the produced output depends solely on existing or present conditions of the inputs.

  • Can be implemented using logic gates exclusively.

  • Input Combinations Formula: The number of possible input combinations shown in rows of a truth table is determined by $2^N$, where $N$ is the number of inputs.

• Sequential Logic:

  • Refers to logic whose operation requires some form of memory device (such as flip-flops and latches).

  • Outputs depend not only on current existing or present input conditions, but also on previous input conditions.

  • 
    

Fundamentals of Logic Gates and Logic Families

• General Logic Gate Concepts:

  • Logic gates serve as the foundational building blocks in digital electronics.

  • Regardless of the underlying technology family (CMOS or TTL), a logic gate is internally composed of an electronic circuit (usually transistor-based) designed to provide a preset logic function.

  • Terminal Structure: Logic gates feature exactly one output terminal. Except for the NOT gate (which has one input), logic gates may have two or more input terminals.

• Input and Output Signal Conditions:

  • Input Statuses:

  • High Logic Level ($1$)

  • Low Logic Level ($0$)

  • Don't Care Status ($x$): Indicates that a particular input has no effect on the circuit output.

  • Output Statuses:

  • High Logic Level ($1$)

  • Low Logic Level ($0$)

  • Indeterminate Condition: An unpredictable output condition caused by specific circuit design limitations (e.g., when both inputs to an active-high SR flip-flop are driven high simultaneously).

• Truth Table Definition:

  • A tabulated list displaying all possible input and output combinations for a given logic circuit.

  • For an $N$--input device, there are exactly $2^N$ possible input/output combination rows.

• 
  

  • $V_{IL(\max)} = 0.8\,\text{V}$

  • Advanced Low-Power Schottky TTL ($74ALS$ Series):

  • Propagation Delay: $4\,\text{ns}$

  • Power Dissipation: $1.2\,\text{mW}$

  • Maximum Clock Rate: $70\,\text{MHz}$

  • Fan-out (Same Series): $20$

  • $V_{OH(\min)} = 2.5\,\text{V}$

  • $V_{OL(\max)} = 0.5\,\text{V}$

  • $V_{IH(\min)} = 2.0\,\text{V}$

  • $V_{IL(\max)} = 0.8\,\text{V}$

  • Fast TTL ($74F$ Series):

  • Propagation Delay: $3\,\text{ns}$

  • Power Dissipation: $6\,\text{mW}$

  • Maximum Clock Rate: $100\,\text{MHz}$

  • Fan-out (Same Series): $33$

  • $V_{OH(\min)} = 2.5\,\text{V}$

  • $V_{OL(\max)} = 0.5\,\text{V}$

  • $V_{IH(\min)} = 2.0\,\text{V}$

  • $V_{IL(\max)} = 0.8\,\text{V}$

Inverter (NOT Gate) Integrated Circuits Matrix

• Comprehensive Device Catalog for Inverters:

  • $7404$ (TTL): Hex Inverter

  • $74HC04$ (CMOS): Hex Inverter

  • $74HCU04$ (CMOS): Unbuffered Hex Inverter

  • $74LS04$ (LS TTL): Hex Inverter

  • $74LS05$ (LS TTL): Hex Inverter with Open-Collector (o.c.) outputs

  • $7406$ (TTL): Hex Inverter with Open-Collector (o.c.) outputs

  • $74LS14$ (LS TTL): Hex Schmitt Inverter

  • $74HC14$ (CMOS): Hex Schmitt Inverter

  • $4049UB$ (CMOS): Unbuffered Hex Inverting Buffer

  • $74HC4049$ (CMOS): Hex Inverter

  • $4069UB$ (CMOS): Unbuffered Hex Inverter

  • $4502B$ (CMOS): Hex 3-state Inverter

  • $40106B$ (CMOS): Hex Schmitt Inverter

  • $74LS240$ (LS TTL): Octal 3-state Schmitt Inverter

  • $4009$ (CMOS): Hex Inverting Buffer

Detailed Specifications of Standard Logic Gates

• Timing Diagram Principles:

  • Displays truth table behavior graphically over time.

  • Inputs and outputs are vertically aligned; horizontal axis denotes state changes across cycles or periods ($T_1, T_2, T_3, T_4, T_5$).

  • Frame durations ($T_n$) may or may not be equal.

  • In combinational logic, time denotes non-absolute period intervals when input conditions occur (unlike sequential logic where time represents absolute microsecond or second points).

• Inverter (NOT Gate):

  • Function: Complements the input logic signal (equivalent to 1's complement). Input $0 \rightarrow$ Output $1$; Input $1 \rightarrow$ Output $0$

  • Schematic Symbol: Triangle with an inversion bubble at the output tip. A triangle without an inversion bubble represents a non-inverting buffer or driver.

  • Electrical Switching Analogue: A normally closed switch connected in parallel across the output load.

  • Common IC Package: $7404$ / $74LS04$ (14-pin DIP with 6 inverters; Pin 14 = $+V_{CC}$, Pin 7 = GND).

• OR Gate:

  • Function: Accepts 2 or more inputs. Output is high ($1$) when at least one input is $1$. Output is low ($0$) only when all inputs are $0$

  • Truth Table (2-Input): $0,0 \rightarrow 0$; $0,1 \rightarrow 1$; $1,0 \rightarrow 1$; $1,1 \rightarrow 1$

  • Boolean Expression: $X = A + B$

  • Electrical Switching Analogue: Parallel normally open switches in series with power supply and load.

  • Common IC Packages:

  • $7432$ / $74LS32$: Quad 2-Input OR Gate

  • $4071$: Quad 2-Input OR Gate

  • $4072$: Dual 4-Input OR Gate

  • $4075$: Triple 3-Input OR Gate

• AND Gate:

  • Function: Accepts 2 or more inputs. Output is high ($1$) only when all inputs are high. Output is low ($0$) if any input is low.

  • Truth Table (2-Input): $0,0 \rightarrow 0$; $0,1 \rightarrow 0$; $1,0 \rightarrow 0$; $1,1 \rightarrow 1$

  • Boolean Expression: $X = A \cdot B$ or $X = AB$

  • Electrical Switching Analogue: Series normally open switches in series with power supply and load.

  • Common IC Packages:

  • $7408$ / $74LS08$: Quad 2-Input AND Gate

  • $4073$: Triple 3-Input AND Gate

  • $4081$: Quad 2-Input AND Gate

  • $4082$: Dual 4-Input AND Gate

• NOR Gate (NOT-OR):

  • Function: Consists of an OR gate followed by an inverter. Output is high ($1$) only when all inputs are at logic low ($0$). Output is low ($0$) if at least one input is high.

  • Truth Table (2-Input): $0,0 \rightarrow 1$; $0,1 \rightarrow 0$; $1,0 \rightarrow 0$; $1,1 \rightarrow 0$

  • Boolean Expression: $X = \overline{A + B}$

  • Electrical Switching Analogue: Series normally closed switches connected across the load.

  • Common IC Packages:

  • $7402$ / $74LS02$: Quad 2-Input NOR Gate

  • $4000$: Dual 3-Input NOR Gate

  • $4001$: Quad 2-Input NOR Gate

  • $4002$: Dual 4-Input NOR Gate

• NAND Gate (NOT-AND):

  • Function: Consists of an AND gate followed by an inverter. Output is low ($0$) only when all inputs are high ($1$). Output is high ($1$) if any input is low.

  • Truth Table (2-Input): $0,0 \rightarrow 1$; $0,1 \rightarrow 1$; $1,0 \rightarrow 1$; $1,1 \rightarrow 0$

  • Boolean Expression: $X = \overline{A \cdot B}$

  • Electrical Switching Analogue: Parallel normally closed switches connected across the load.

  • Common IC Packages:

  • $7400$ / $74LS00$: Quad 2-Input NAND Gate

  • $7410$: Triple 3-Input NAND Gate

  • $7420$: Dual 4-Input NAND Gate

  • $4011$: Quad 2-Input NAND Gate

• Exclusive-OR (XOR) Gate:

  • Function: Produces a high logic output ($1$) only when an odd number of inputs are high (odd parity). Output is low ($0$) when inputs are both low or both high (even parity).

  • Truth Table (2-Input): $0,0 \rightarrow 0$; $0,1 \rightarrow 1$; $1,0 \rightarrow 1$; $1,1 \rightarrow 0$

  • Truth Table (3-Input): $000 \rightarrow 0$; $001 \rightarrow 1$; $010 \rightarrow 1$; $011 \rightarrow 0$; $100 \rightarrow 1$; $101 \rightarrow 0$; $110 \rightarrow 0$; $111 \rightarrow 1$

  • Boolean Expression: $X = A \oplus B = A \cdot \overline{B} + \overline{A} \cdot B$

  • Applications: Code checking, code conversion, arithmetic binary addition.

  • Common IC Packages:

  • $7486$ / $74LS86$: Quad 2-Input XOR Gate

  • $4030$: Quad 2-Input XOR Gate

  • $4070$: Quad 2-Input XOR Gate

• Exclusive-NOR (XNOR / ENOR) Gate:

  • Function: Complement of the XOR gate. Output is high ($1$) when inputs are identical (even parity). Referred to as the Equality Gate. Output is low ($0$) when inputs differ (odd parity).

  • Truth Table (2-Input): $0,0 \rightarrow 1$; $0,1 \rightarrow 0$; $1,0 \rightarrow 0$; $1,1 \rightarrow 1$

  • Truth Table (3-Input): $000 \rightarrow 1$; $001 \rightarrow 0$; $010 \rightarrow 0$; $011 \rightarrow 1$; $100 \rightarrow 0$; $101 \rightarrow 1$; $110 \rightarrow 1$; $111 \rightarrow 0$

  • Boolean Expression: $X = \overline{A \oplus B} = A \cdot B + \overline{A} \cdot \overline{B}$

  • Common IC Packages:

  • $74266$ / $74LS266$: Quad 2-Input XNOR Gate

  • $4077$: Quad 2-Input Exclusive NOR Gate

Summary of Universal 2-Input Logic Gate Behaviors

• NOT Gate: Any input produces an opposite output state.

• OR Gate: High logic level on any input produces a high logic output.

• NOR Gate: High logic level on any input produces a low logic output.

• AND Gate: Low logic level on any input produces a low logic output.

• NAND Gate: Low logic level on any input produces a high logic output.

• XOR Gate: Output is high when one and only one input is high (high output if the total number of $1$s is odd).

• XNOR Gate: Output is high when inputs are equal (high output if the total number of $1$s is even).

Practical Applications of Logic Gates

• Applications of NOT Gates:

  • Used for switch state indicator inversion (e.g., Change Switch Position Off = Logic $1$ State, On = Logic $0$ State feeding LED Cathode driver circuit).

• Applications of OR Gates:

  • Doorbell system triggering: Actuators connected to "Front Door" or "Back Door" pushbuttons activate the single doorbell output when either button is depressed.

• Applications of AND Gates:

  • Industrial machinery safety interlock: Power converter activation requires Part Sensor signal AND Safety Switches signal simultaneously.

• Applications of NOR Gates:

  • Mixing tank outlet control: Outlet valve logic remains deactivated when any sensor (Start Sensor, Level Sensors) detects high status (output active only when all input conditions are $0$).

• Applications of NAND Gates:

  • Automobile interior dome light system: Actuated when any car door opens, pulling the corresponding NAND input to logic low to produce a high logic light output.

• Applications of XOR Gates:

  • Dual-location stairway light control: Uses two 3-way switches (Switch A and Switch B). Toggling either switch flips the parity, thereby turning the stairway lamp on or off.

• Applications of XNOR Gates:

  • Water level monitoring and alarm activation: Evaluates signals from a High Level Float and a Low Level Float. Triggers warning lamp / alarm output under specific matched float equality logic levels.

Discrete Logic Gate Implementations

• Transistor Inverter (NOT Gate):

  • Circuit Structure: Single NPN bipolar junction transistor (e.g., $2N2222$).

  • Resistors: $3\,\text{k}\Omega$ base input resistor, $3\,\text{k}\Omega$ collector pull-up resistor connected to $+5\,\text{V}$ supply.

  • Operation: Base high conducts transistor to ground (output $0\,\text{V}$); base low cuts off transistor (output pulled up to $+5\,\text{V}$).

• Discrete OR Gate Implementations:

  • Diode OR Gate: Diodes connected to inputs $A$ and $B$, cathodes joined to load resistor $R_L = 10\,\text{k}\Omega$ driving a $2N3904$ NPN transistor buffer stage with LED indicator and $330\,\Omega$ current limit resistor ($R_{Lim}$).

  • Transistor OR Gate: Parallel NPN transistors ($2N2222$) with separate $3\,\text{k}\Omega$ base resistors ($A$ and $B$) and shared collector output network.

• Discrete AND Gate Implementations:

  • Transistor AND Gate: Series-connected NPN transistors ($2N2222$) with base inputs $A$ and $B$ via $3\,\text{k}\Omega$ resistors and $+5\,\text{V}$ collector pull-up.

• Discrete NOR Gate Implementation:

  • Circuit Structure: Two NPN transistors ($2N2222$) wired in parallel.

  • Resistors: Inputs $A$ and $B$ fed through $3\,\text{k}\Omega$ base resistors; collectors tied together to a common $3\,\text{k}\Omega$ pull-up resistor connected to $+5\,\text{V}$.

  • Operation: Triggering either base pulls output voltage to ground.

• Discrete NAND Gate Implementation:

  • Circuit Structure: Two NPN transistors ($2N2222$ / $2N3904$) wired in series.

  • Resistors: Base inputs fed via $10\,\text{k}\Omega$ resistors; top collector pulled up to $+5\,\text{V}$ or $+6\,\text{V}$ via $4.7\,\text{k}\Omega$ or $10\,\text{k}\Omega$ resistor.

  • Operation: Output grounds only when both transistor bases are driven high simultaneously.

• Discrete XOR Gate Implementation:

  • Components: Transistor $Q_1$, Diodes $D_2, D_3, D_4, D_5$, Resistors $R_1 = 1\,\text{k}\Omega$, $R_2 = 10\,\text{k}\Omega$, $R_3 = 100\,\Omega$, Switches $SW_1, SW_2, SW_3$, DC Voltage source $B_1 = 12\,\text{V}$.

• Discrete XNOR Gate Implementation:

  • Components: Transistor $Q_2$, Diodes $D_7, D_9$, Resistors $R_4 = 1\,\text{k}\Omega$, $R_5 = 1\,\text{k}\Omega$, $R_6 = 10\,\Omega$, $R_7 = 10\,\Omega$, Switches $SW_4$, DC Voltage source $B_2 = 12\,\text{V}$.

Equivalent Logic Circuit Configurations and Boolean Transformations

• XOR Gate Equivalent Logic Constructions:

  • Standard Logic Gate Design #1: $X = A \cdot \overline{B} + \overline{A} \cdot B$ (constructed using 2 NOT gates, 2 AND gates, and 1 OR gate).

  • Standard Logic Gate Design #2 (NAND-Only): $X = \overline{\overline{A \cdot \overline{A \cdot B}} \cdot \overline{B \cdot \overline{A \cdot B}}}$

• XNOR Gate Equivalent Logic Constructions:

  • Standard Logic Gate Design #1: $X = A \cdot B + \overline{A} \cdot \overline{B}$

  • Standard Logic Gate Design #2: $X = \overline{(A + B) \cdot \overline{A \cdot B}} = (A \cdot B) + (\overline{A + B})$

  • Operational Relationship: Placing an inverter at the output of an XNOR equivalent circuit yields an XOR output, and placing an inverter at the output of an XOR equivalent circuit yields an XNOR output.

• Gate Conversions Using Inverters (De Morgan's Laws):

  • Inverting Outputs:

  • AND Gate with Inverted Output $=\text{NAND}$

  • OR Gate with Inverted Output $=\text{NOR}$

  • Inverting Inputs:

  • AND Gate with Inverted Inputs $=\text{NOR}$ (i.e., $\overline{A} \cdot \overline{B} = \overline{A + B}$)

  • OR Gate with Inverted Inputs $=\text{NAND}$ (i.e., $\overline{A} + \overline{B} = \overline{A \cdot B}$)

  • NAND Gate with Inverted Inputs $=\text{OR}$ (i.e., $\overline{\overline{A} \cdot \overline{B}} = A + B$)

  • NOR Gate with Inverted Inputs $=\text{AND}$ (i.e., $\overline{\overline{A} + \overline{B}} = A \cdot B$)

  • Inverting Inputs and Outputs (Double Negation Equivalences):

  • Inverters at Inputs + AND Gate + Output Inverter $=\text{OR}$

  • Inverters at Inputs + OR Gate + Output Inverter $=\text{AND}$

  • Inverters at Inputs + NAND Gate + Output Inverter $=\text{NOR}$

  • Inverters at Inputs + NOR Gate + Output Inverter $=\text{NAND}$

Universal Gate Synthesis (NAND and NOR)

• Universal NAND Gate Principles:

  • The 2-input NAND gate is classified as a universal gate because combinations of NAND gates can implement all 6 other logic gate functions (NOT, AND, OR, NOR, XOR, XNOR).

  • SSD (Small Scale Integration) designs frequently utilize NAND gates exclusively.

  • Basic Logic Gate Synthesis Using NAND Gates:

  • NOT Gate: Connect inputs together: $X = \overline{A \cdot A} = \overline{A}$

  • AND Gate: NAND gate followed by a NAND inverter: $X = \overline{\overline{A \cdot B}} = A \cdot B$

  • OR Gate: Invert inputs using NAND inverters, then feed into a NAND gate: $X = \overline{\overline{A} \cdot \overline{B}} = A + B$

  • NOR Gate: NAND OR-configuration followed by a NAND inverter: $X = \overline{A + B}$

  • XOR Gate: Constructed using 4 NAND gates.

  • XNOR Gate: Constructed using 5 NAND gates (XOR configuration followed by a NAND inverter).

• Universal NOR Gate Principles:

  • The 2-input NOR gate is also a universal gate capable of representing all other logic gate functions.

  • Basic Logic Gate Synthesis Using NOR Gates:

  • NOT Gate: Connect inputs together: $X = \overline{A + A} = \overline{A}$

  • OR Gate: NOR gate followed by a NOR inverter: $X = \overline{\overline{A + B}} = A + B$

  • AND Gate: Invert inputs using NOR inverters, then feed into a NOR gate: $X = \overline{\overline{A} + \overline{B}} = A \cdot B$

  • NAND Gate: NOR AND-configuration followed by a NOR inverter: $X = \overline{A \cdot B}$

• Circuit Synthesis and Conversion Examples:

  • Synthesis Example 1: Convert $X = (A \cdot B) + C$ to a NAND-only logic circuit.

  • Conversion Steps: Apply double negation and De Morgan's Law: $X = \overline{\overline{(A \cdot B) + C}} = \overline{\overline{A \cdot B} \cdot \overline{C}}$

  • Circuit Implementation: First NAND gate computes $\overline{A \cdot B}$, second NAND inverter computes $\overline{C}$, third NAND gate combines inputs to produce $X$

  • Synthesis Example 2: High output required when either $A$ or $B$ is high, but $C$ is low.

  • Initial Expression: $X = (A + B) \cdot \overline{C}$

  • Standard Gate Logic: 1 OR gate for $(A+B)$, 1 NOT gate for $C$, 1 AND gate to multiply.

  • NAND-Only Conversion: Convert operations into products: $A + B = \overline{\overline{A} \cdot \overline{B}}$, giving $X = \overline{\overline{\overline{\overline{A} \cdot \overline{B}} \cdot \overline{C}}}$

  • Synthesis Example 3: Simplification and synthesis of $X = [(A + (A + B)) \cdot (B + (B + C))]$ using NAND gates only.

  • Boolean Simplification Step 1: $A + (A + B) = A + B$

  • Boolean Simplification Step 2: $B + (B + C) = B + C$

  • Boolean Simplification Step 3: $X = (A + B) \cdot (B + C) = B + A \cdot C$

  • NAND Conversion: Apply double negation: $X = \overline{\overline{B + A \cdot C}} = \overline{\overline{B} \cdot \overline{A \cdot C}}$

  • Implementation: 1 NAND gate computes $\overline{A \cdot C}$, 1 NAND inverter computes $\overline{B}$, 1 final NAND gate produces output $X$

  • Synthesis Example 4: Convert $X = (A + B) \cdot C$ to a NOR-only logic circuit.

  • Conversion Steps: Apply double negation to convert multiplication to addition terms: $X = \overline{\overline{(A + B) \cdot C}} = \overline{\overline{A + B} + \overline{C}}$

  • NOR-Only Implementation: NOR gate computes $\overline{A + B}$, NOR inverter computes $\overline{C}$, combined in a NOR gate, followed by a final NOR inverter output stage.