Instruction Cycles and Control Units Notes

Why Study Instruction Cycles and Control Units?

  • Control units are central to modern computers.

  • Understanding control units is essential because all modern machines perform instruction fetch, decode, and execute cycles.

  • Programming in Assembly Language requires understanding CPU operation, especially instruction fetch/decode/execute cycles.

  • Machine performance depends critically on the control unit design.

  • Real-time programming requires understanding the fetch/decode/execute cycle and its impact on interrupt handling.

Basic Machine Organization

  • Central Processing Unit (CPU)

    • Arithmetic Logic Unit (ALU)

    • Control Unit

    • Register Files

  • Main Memory

    • Memory Controller

    • Memory Arrays

  • Input/Output (I/O)

    • I/O Controllers

    • I/O Devices

  • Diagram: CPU interacts with Memory and I/O.

Program Execution

  • The CPU fetches instructions (binary executable, e.g., .exe file) from main memory.

    • Data vs. Code: Distinction between what is processed and the instructions to process it.

  • Each instruction (e.g., add, load, store) must be decoded in the CPU.

  • After decoding, the instruction is executed by issuing commands to the ALU and manipulating operands in CPU registers.

  • Once an instruction is completed, the next one is fetched from memory.

  • This cycle repeats for every instruction in the code.

Instruction Fetch

  • Process

    • The Program Counter (PC) points to the instruction in memory.

    • The instruction is loaded into the Instruction Register (IR).

Instruction Decoding

  • The instruction in the IR is decoded to determine the operation to be performed.

Instruction Execution

  • Process

    • The Control Unit decodes the instruction and then executes it by activating CPU components in the proper order.

Simplistic CPU Architecture

  • Components

    • Program Counter: Stores the address of the next instruction.

    • Instruction Register: Stores the current instruction being executed.

    • Accumulator: Stores intermediate results.

    • ALU: Performs arithmetic and logical operations.

    • Memory Address Register: Stores the address to read from or write to in memory.

    • Memory Data Register: Stores the data being read from or written to memory.

    • Control Unit: Manages the execution of instructions.

  • Buses

    • Data Bus: Carries data between components.

    • Address Bus: Carries memory addresses.

    • Control Bus: Carries control signals.

CPU Internals and ALU

  • Components

    • Arithmetic Logic Unit/Register File

    • Status Register

    • Logical Shifter

    • Logical Complementer

    • Adder (Subtract)

    • Multiplier

    • Logical Operations

    • Register File

    • Internal CPU Bus

Practical Simple CPU Architecture

  • Components

    • Program Counter

    • Instruction Register

    • Accumulator

    • ALU

    • Y Register

    • Z Register

    • Memory Address Register

    • Memory Data Register

    • Control Unit

Control Unit

  • The Control Unit uses control lines to manage the CPU's operations.

Control Unit Activation of Components

  • Components controlled: ALU, Registers (Y, Z, Accumulator), Memory (Address, Read, Write), Instruction Register, Program Counter.

Control Unit Operations

  • Instruction Fetch Cycle

    • T0: Program Counter -> CPU Bus; CPU Bus -> Memory Address Register

    • T1: Memory Address Register -> Address Bus; Memory Read -> Control Bus

    • T2: Data Bus -> Memory Read Data Register

    • T3: Memory Read Data Register -> CPU Bus; CPU Bus -> Instruction Register

  • Instruction Execution Cycle (e.g., ADD 7, ACC)

    • T4: Instruction Register -> CPU Bus; CPU Bus -> Y Register

    • T5: Accumulator Register -> CPU Bus; CPU Bus -> ALU; ALU Operation

    • T6: ALU -> Z Register

    • T7: Z Register -> Accumulator Register

Control Unit Implementation

  • The Control Unit executes an algorithm that implements the instruction.

  • Different Ways to Build a Control Unit

    • Microcoded control unit (CISC)

    • Hardwired logic (RISC)

  • Each step (t0, t1, …, t7) requires a specific combination of control signal values.

  • These make up the "microprogram," stored in a "control store."

  • Every "microinstruction" occupies a "microword" in the control store.

  • Logic in the Control Unit steps through the microprogram, using a "microprogram counter" to point to the location in the "control store" of the control word to be used.

  • Part of the microword contains the control store address of the next microword, which is loaded into the microprogram counter.

  • Complicated microprograms can be implemented (e.g., polynomial evaluation).

  • Control stores are usually ROM (Read Only Memory) but were often RAM, loaded before booting.

Control Unit - Horizontal

  • Horizontal Control Store Structure: Each bit is buffered to the Control Bus.

    • Includes signals like PC Rd, MWr, MRd, IR Ld, ZOut, Yin, and the next microword address.

    • Microprogram Counter

Types of Control Units

  • Horizontal Microcode

  • Vertical Microcode

Horizontal Microcode

  • If every bit in the control store microword maps directly into a control signal value, the CPU has "horizontal microcode."

  • Horizontal microcode can be inefficient since often only part of the microword is used in any microinstruction.

  • Microwords can be as large as hundreds of bits in complex designs.

  • It can be accessed quickly with few limits in programming.

Vertical Microcode

  • An alternative to horizontal microcode.

  • A decoder is placed between the control store and the control signals.

  • The control store entry for the microinstruction is smaller than the number of control signals:

    • Decoder maps NN control store bits into MM signals, where M > N.

  • Higher packing density in control store allows for a smaller and cheaper device.

  • Decoder introduces delay, hence performance loss, and less flexibility in microprograms.

Horizontal vs. Vertical Microcode

  • Where storage for microcode is not too expensive, horizontal microprogramming is favored since microprograms are easier to debug and test, and performance is better.

  • Some dangerous combinations are possible!

  • In early CISC microprocessors, chip real estate for the control store was very difficult to find, therefore vertical microcoding was a very popular technique.

  • This was despite the performance penalty and much lesser flexibility in microcode programming.

Horizontal vs. Vertical Microcode Example

  • Scenario: We have 5 registers that can output to the CPU bus:

    • Instruction Register (IR)

    • Program Counter (PC)

    • Memory Read Register (MRR)

    • Accumulator (ACC)

    • Z Register (Z)

  • Since only one of the 5 may be asserted at any time, using 5 bits in the microword is wasteful, as most combinations don't make sense.

  • In a vertically microcoded design, these five bits would be encoded into 3 bits in the microword.

  • A decoder would assert one of five control lines when it sees the 3-bit "source register" code.

Hybrid Microcode

  • It's feasible to use “hybrid” microcoding, where some control store fields are encoded, and others are not.

  • This provides the flexibility of horizontal microcode but yields a smaller control store than a pure horizontally microcoded design.

  • Its limitation is that the time delay of decoding is still incurred, so the smaller control store is acquired at a price in performance.

Hardwired Control Units

  • Microprogramming was the preferred technique between 1960 and 1985.

  • Newer architectures use hardwired control units, where the instruction is decoded directly, and the control signals are driven by dedicated control logic.

  • Hardwired designs are potentially simpler and faster but more difficult to debug and modify, requiring a large simulation effort.

  • Hardwired designs are often based on a state machine.

Hardwired Control – State Machine Design

  • Components: Next State Logic, Next State Register, Clock, Machine State (e.g., IR value, ACC < 0), Output Logic.

Simple CPU Design

  • Instruction Format: Instructions are stored in a very simple format.

  • The top 3 bits of the 16-bit instruction hold an opcode, and the remaining 13 bits are used to address memory.

The Finite State Machine

  • All control signals are generated using a finite state machine.

  • The finite state machine consists of:

    • Current State Register

    • Next State Logic

    • Output Logic

Example - Fetch Phase

  • Step 1: PC → MAR

  • Step 2: Increment PC

  • Step 3: Read Memory

  • Step 4: MDR → IR

Example - Load the Accumulator

  • Step 1: IR → MAR

  • Step 2: Read Memory

  • Step 3: Clear Accumulator

  • Step 4: MDR + Acc → Acc

The State Transition Chart

  • Defines transitions between states based on opcodes (LDA, STA, ADD, AND, SKP, JMP, JMI) and conditions (Acc > 0, Acc ≤ 0).

  • States include operations like PC → MAR, Increment PC, Read Memory, MDR → IR, IR → MAR, Clear Acc, and MDR + Acc → Acc.

Output Variables

  • Look at the meaning of signals to determine which signals should be 0 and 1.

Working out the transition equations

Deriving the next state equations

Working out the output values

Forming output equations

Example – Demonstration CPU Made From Individual Transistors

  • http://www.megaprocessor.com/index.html

  • The Megaprocessor is built from transistors; instead of using tiny ones integrated on a silicon chip, it uses discrete individual ones.

Summary

  • Operation of instruction cycles

  • Control Units

  • Horizontal vs Vertical

  • Examples of operation

  • Next: More on CPU internals