Digital Systems & Computer Architecture – Adders, Subtractors, Flip-Flops & Registers

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Combinational Logic

Full Adder (FA)

• Definition
  • Adds three binary bits simultaneously (A, B, $C_{in}$).
  • Outputs: Sum (S) and Carry-out ($C_o$).
• Inputs/Outputs Roles
  • A, B → present significant bits.
  • $C_{in}$ → carry from previous stage.
  • S → result bit; $C_o$ → carry to next higher stage.
• Truth Table
  • 8 combinations show when a carry propagates.
• Boolean Derivations
  • Sum (canonical SOP):
    $S = A'B' C<em>{in} + A' B C</em>{in}' + A B' C<em>{in}' + A B C</em>{in} = A \oplus B \oplus C_{in}$
  • Carry:
    $C<em>o = AB + B C</em>{in} + A C_{in}$
• Implementation Variants
  • Two Half-Adders + OR gate.
  • Direct gate-level: XOR for S, AND/OR network for $C_o$.
• Significance
  • Fundamental cell of ripple-carry adders, ALUs, parity checkers.

Half Subtractor (HS)

• Performs X − Y producing Difference (D) and Borrow (B).
• Borrow bit weight $=-2$; Difference weight $=+1$.
• Boolean expressions
  • $D = X \oplus Y$
  • $B = X' Y$ (borrow when minuend 0 and subtrahend 1).

Full Subtractor (FS)

• Handles three inputs: X (minuend), Y (subtrahend), Z (previous borrow).
• Executes $X - Y - Z$.
• Boolean expressions
  • $D = X \oplus Y \oplus Z$
  • $B = X' (Y \oplus Z) + Y Z = X' Y + X' Z + Y Z$
• Built from two half-subtractors + OR gate.

Sequential Logic – Flip-Flops

General Features

• Store one bit; two stable states (Q, $\overline{Q}$).
• Built with cross-coupled NAND/NOR; edge-triggered versions use gating.

SR Flip-Flop

• Inputs: S (set), R (reset) + asynchronous PR/CLR.
• Truth Table highlights invalid S=R=1.
• PR/CLR set deterministic power-on state.

JK Flip-Flop

• J acts like S; K like R; resolves SR invalidity.
• State table includes toggle when J=K=1.
• Race-Around: with wide clock pulse & J=K=1, output toggles rapidly; avoided via master-slave or edge-triggered design.

D Flip-Flop

• Single input D. Characteristic: $Q_{n+1}=D$ on clock edge.
• Provides level-to-edge conversion; ideal for pipelining.

T Flip-Flop

• T="toggle". Behaviour: T=0→hold, T=1→invert on every clock.
• Frequency divider: $f<em>{out}=\frac{f</em>{clk}}{2}$.

Flip-Flop Conversions

• Example: implement T with D ⇒ $D = T \oplus Q$.
• Conversion table supplied links SR, JK, D, T excitations.

Applications

• Counters, frequency dividers, shift registers, storage/bounce elimination, memory cells.

Registers

Concept

• n flip-flops grouped to store n-bit word; fastest CPU storage.
• Operates within Fetch–Decode–Execute cycle.

Typical CPU Registers (16-bit example)

• Program Counter (PC): address of next instruction.
• Memory Address Register (MAR): holds memory address reference.
• Memory Data/Buffer Register (MDR/MBR): bidirectional data buffer.
• Instruction Register (IR): current instruction.
• Accumulator (AC): primary arithmetic result.
• Temporary Register (TR): scratchpad.
• Data Register (DR), INPR, OUTR: I/O staging.
• Index Register (XR): address modification.

Register Operations

• Fetch: PC→MAR, Memory→MDR→IR.
• Decode: control unit interprets opcode.
• Execute: ALU acts; results stored back (often AC or memory).

Key Formulae Recap

• Full Adder: $S = A \oplus B \oplus C<em>{in}$ ; $C</em>o = AB + B C<em>{in} + A C</em>{in}$
• Half Subtractor: $D = X \oplus Y$ ; $B = X' Y$
• Full Subtractor: $D = X \oplus Y \oplus Z$ ; $B = X' Y + X' Z + Y Z$
• T-Flip-Flop frequency division: $f<em>{out} = \frac{f</em>{clk}}{2}$

Exam-Prep Checklist

• Memorise FA truth table & simplifications.
• Draw FA with two half-adders.
• Derive subtractor borrow equations.
• Distinguish latch vs edge-triggered FF.
• Explain race-around & remedies.
• Apply conversion formulas between FF types.
• Sketch CPU datapath registers and describe fetch–decode–execute.