Embedded Systems_Course_L5_EPT
Embedded Systems
Definition and Overview
Microprocessor Architecture
Basic definition and structure of microprocessor architectures.
Calculator Basic Architecture
Address Bus: Transfers address signals.
Data Bus: Transfers data signals.
Control & Command Bus: Carries control signals.
CPU: Central Processing Unit, manages program operation.
Memory: Storage for data and programs.
I/O Interfaces: Allow communication with peripherals.
Buses Definition
Address Bus: Unidirectional for address signals.
Data Bus: Bidirectional for data transfer.
Control & Command Bus: Carries read/write commands and interruptions from CPU.
CPU Organization
Logic Circuit: Program-based operation.
Registers: Support for instruction codes, data, and addresses.
ALU (Arithmetic & Logic Unit): Performs arithmetic and logic operations.
Control Unit: Decodes instructions and supervises operations.
ALU Description
Performs Arithmetic Operations: Addition, Subtraction, Increment/Decrement.
Performs Logical Operations: AND, OR, XOR, Rotation.
CPU Registers
Accumulator: Holds operands and results during ALU operations.
State Register (SR): Displays ALU operation status.
Instruction Register (IR): Contains currently executing instruction code.
Program Counter (PC): Keeps track of the next instruction's address.
CPU Control Unit
Function: Manages CPU operations and instruction execution.
Steps: Instruction extraction, decoding, execution, and sequencing.
Memory Definition
Used for data & program storage, can be ROM or RAM.
Organization: Memory structured in bits and bytes organized in words.
Memory Access Mode
Reading: CPU activates read on the address bus.
Writing: CPU places data on the bus and activates write.
Input/Output Interface
Purpose: Establish communication between CPU and peripheral units.
Processes: Similar to memory access operations.
Advanced Architectures
Discusses different classes of microprocessors.
Microprocessor Classes
Microcontrollers: Compact integrated circuit with memory & I/O.
DSPs (Digital Signal Processors): Optimized for real-time processing.
CISC (Complex Instruction Set Computer): Aims for versatile instruction processing.
RISC (Reduced Instruction Set Computer): Simplifies instructions for efficiency.
Microprocessor Architecture Families
Von Neumann Architecture: Shared memory for data & instructions.
Harvard Architecture: Separate memory for program and data.
Instruction Sets
Overview of ARM and Thumb instruction sets, including conditional execution and loading mechanisms.
Cortex-M4 Processors
Introduced in 2010, focuses on signal processing efficiency and low power consumption.
Architecture based on RISC principles, supports various instruction sets.
Features include multiple interrupts and power management strategies.
ARM Cortex-M4 Processor Features
List of performance features, instruction set specifics, memory maps, and types of registers.
Memory Management
Overview of memory maps and regions within the Cortex-M4 architecture.
Assembly Programming Language
Overview of assembly language structure, data directives, and translation from symbolic to executable code.
Summary of Key Concepts
RISC vs CISC, Processor Modes, Pipeline Technique, and ARM Cortex-M4 specifics.