Yur

CPU

fetches instructions, decodes them, performs a sequence of operations

Datapath

network of registers and arithmetic and logic units connected by busses

Control Unit

sequences the operations of an instruction

Registers

store data temporarily, one D flip-flop per bit, clock pulse used to set data

The Arithmetic Logic Unit (ALU)

This unit does addition, multiplication, division, etc.

Status Register

may be affected by ALU activity (carry bit, overflow bit, etc)

Program Counter (PC)

stores the location in RAM of the next fetch

A Bus

a set of wires that connect components. May be 16, 32 or 64 bits wide

Bus Arbitration

components may to request access to the bus and may have to wait if it is busy.

Point-to-point Bus

some busses are not shared, like from a serial port to a printer.

Multipoint Bus

connects several components

Bus Protocol

set of rules for using the bus.

Processor-Memory buses

short, high-speed buses connecting CPU components

I/O buses

longer, slower buses that connect peripherals

Backplane Bus

built into chassis, can connect various components

Expansion Buses

for expansion cards

Synchronous Buses

synchronized by clock cycles

Asynchronous Buses

coordinated by control lines

Clocks

Within CPU clocks synchronize all components. Most instructions require several clock cycles to finish their steps. Some instructions require more cycles.

Clock Frequency

a number that is slow enough to allow all the combinational logic gates to reach their final values.

Interface

hardware to handle communication with devices

Memory-Mapped I/O

writing to RAM causes changes in the device, like the pixels on a monitor.

Instruction-Based I/O

CPU writes instructions to device to change its state

Byte addressable

each byte has its own address

Word addressable

each word has its own address (words can be 16, 32 or 64 bits)

Memory Interleaving

how RAM chips are combined to provide whole memory

Low-Order interleaving

low-order bits are used to select the module

High-Order interleaving

high-order bits are used to select the module

Interrupt handling

actions performed in response to interrupts

Maskable interrupts

interrupts that are not urgent and can wait

Nonmaskable interrupts

interrupts that are urgent and cannot wait

Instruction Set Architecture (ISA)

set of instructions for a machine language

SkipCond 000

AC

SkipCond 400

AC=0

SkipCond 800

AC\>0

Load

0001

Store

0010

Add

0011

Subt

0100

Input

0101

Output

0110

Halt

0111

SkipCond

1000

Jump

1001

Register Transfer Notation (RTN)

short hand notation to show movement of data and instructions in a processor, can be used to represent the operation of the fetch-execute cycle

Microoperations

steps to execute and instruction

Operation for Load

MAR ← X

MBR ← M[MAR]

AC ← MBR

Operation for Store

MAR ← X, MBR ← AC

M[MAR] ← MBR

Operation for Add

MAR ← X

MBR ← M[MAR]

AC ← AC + MBR

Operation for Subt

MAR ← X

MBR ← M[MAR]

AC ← AC - MBR

Operation for Input

AC ← InREG

Operation for Output

OutREG ← AC

Operation for Halt

No Operation for this one

Operation for Jump

PC ← X

Fetch

MAR ← PC

IR ← MBR

PC ← PC+1

Interrupt latency

how long it takes to handle an interrupt

Hardware Interrupts

generated by keyboard, mouse, hard drives, memory, timers, etc.

Interrupt Service Routine (ISR)

subroutine to handle an interrupt

Interrupt Request (IRQ)

signal to CPU to handle an interrupt. Each device is assigned a number (IRQ\#) so the CPU can tell which ISR to run.

Interrupt Vector Table

table of addresses of interrupt handlers by IRQ number

Software Interrupts

Cause an interrupt similar to hardware interrupt. Basically causes a subroutine (often in OS) to run to take care of something.

Direct Addressing

address in instruction is address of data

Indirect Addressing

address in instruction is address to find address of data (is a pointer)

Operation for JnS X

MBR ← PC

MAR ← X

M[MAR] ← MBR

MBR ← X

AC ← 1

AC ← AC + MBR

PC ← AC

Operation for Clear

AC ← 0

Operation for AddI

MAR ← X

MBR ← M[MAR]

MAR ← MBR

MBR ← M[MAR]

AC ← AC + MBR

Operation for JumpI X

MAR ← X

MBR ← M[MAR]

PC ← MBR

Operation for LoadI X

MAR ← X

MBR ← M[MAR]

MAR ← MBR

MBR ← M[MAR]

AC ← MBR

Operation for StoreI X

MAR ← X

MBR ← M[MAR]

MAR ← MBR

MBR ← AC

M[MAR] ← MBR

Hardwired Control

decoding of instruction and the following steps all done with combinational logic gates.

Microprogrammed Control

each instruction is reduced to a set of microinstructions that are hardwired.