1.1.1 structure and function of the processor

components of a processor

ALU - completes all the arithmetic and logical operations

CU - component of the processor that directs the CPU,

• accepts/decodes the next instruction

• stores the resulting data back in memory

PC - hold the address of the next instruction to be executed

• if the current instruction is a branch or jump instruction, the address to jump to, copied from the current instruction register (CIR) to the PC.

ACC - stores the results from calculations

MAR - holds the address of a location that is to be read from or written to

MDR - temporarily stores the data that has been read or data that needs to be written

• acts as a buffer between the CPU and RAM

CIR - holds the current instruction being executed, divides into opcode and operand

Bus

data bus

• carries data/instructions between cpu memory, I/O devices

• bi directional

address bus

• carries the memory address from CPU to Memory

• Unidirectional

Control Bus

• carries signals to manage operations of the computer systems

• memory read/write and interrupt requests

Fetch

• Address from the PC is copied to the MAR

• Instruction held at that address is copied to MDR by the data bus -

• Simultaneously, the contents of the PC are increased by 1

• The value held in the MDR is copied to the CIR

Decode

The instruction held in the CIR is decoded. The instruction is split into opcode and operand and the opcode is used to determine the type of instruction and what hardware to use to execute it.

The operand holds either:

• the address of the data to be used with the operation, which is then copied to the MAR

OR:

• the actual data to be operated on, which will be copied to the MDR

• the data to be operated on may be passed to the ALU/accumulator

Execute

The decode instruction is executed

Factors that affect CPU performance

• clock speed

• cache size

• number of cores

clock speed

How many state changes the CPU performs per second

• if a computer has a higher clock speed → execute more instructions per second

• carry out tasks more quickly

number of cores

a core is a processing unit within the CPU → multiple cores mean tasks are carried out more quickly → each core can carry out its own task (parallel processing)

• dual core processor isn’t as fast → time spent organising tasks between cores

• some tasks cannot be split therefore not as quick

cache size

part of primary storage and used to store data/instructions

• closer to the CPU than RAM so faster to retrieve data

• level 1 is best → small/fast for each core

• level 3 slower/longer than level 2 → sits on the motherboard

Pipelining

• Pipelining is the process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously

• While one instruction is being executed, another can be decoded and another fetched.

How does pipelining improve CPU performance

• aimed to reduce the amount of the CPU which is kept idle

• holding appropriate data in a buffer in close proximity to the CPU until it’s required.

• reduces latency

• All parts of the processor can be used at any instant in time

In what case can a pipeline be flushed

• In the case of a branch, the pipeline is flushed

• CPU cannot know for certain which instruction will come next until the branch is evaluated

• If the prediction is wrong, the CPU discovers it is executing the wrong instructions.

• The pipeline is then flushed (emptied) to clear the incorrect operations, and the correct instructions are fetched.

Impact on performance when pipeline is flushed

• Pipeline flushing introduces a delay or "stall

• The time it takes to flush the pipeline and load the correct instructions into the fetch stage temporarily lowers processor throughput

Instruction pipelining

separates instructions into fetching → decoding → executing

Arithmetic pipelining

breaking down the arithmetic operations and overlapping them as they are performed

Harvard architecture

• physically separate memories for instructions/data

• The CPU can fetch an instruction and read/write data at the exact same time
  Use Cases:

• Microcontrollers, digital signal processing (DSP) chips, audio processors, traffic lights, and other dedicated embedded systems.

Von neuman achitecture

• Instructions and data share a single, unified memory space and the same set of buses (communication pathways).
  Use Cases:

• General-purpose computers, laptops, desktop processors, and mobile phones

ADV/ DISADV for harvard + von neuman

von neuman

• cheaper to develop → cu is easier to design

• programs can be optimised in size

DISADV:

• two clock cycles required

• cpu cannot access read/write instructions simultaneously

• pipelining is not possible

hardvard

• quicker → data can be fetched in parallel

• one clock cycle required '

• pipelining is possible

• separate MA used for instructions and data

• Memories can be different sizes, which can make more efficient use of space

DISADV:

• more costly

• It can also result in wasted memory space if one memory block is full while the other sits empty.

diff between von neuman + harvard

• harvard = pipelining is possible

• von neuman = not possible

harvard = physically separate memories for instructions/data

von neuman = Instructions and data share a single, unified memory space and the same set of buses

harvard = two clock cycles

von neuamn = 1 clock cycle

contemporary processors

• Main Memory: Uses Von Neumann architecture (shared memory space for both data and instructions).

• Cache Memory: Uses Harvard architecture (separate physical caches for instructions and data).