Interrupt Handling

What is Programmed IO?

• CPU sits in tight loop until input available or output accepted

• Occupies CPU (busy waiting)

• Possible to have very fast reactions

What is Interrupt Driven IO?

• Hardware signal directly changes program flow

• CPU can do other work or sleep until receiving IO

• Alternative to Programmed IO

What are the four guarantees of a precise interrupt?

• Program Counter preserved

• Everything before PC fully executed

• Nothing beyond PC started

• State of instruction at PC must be known

What does the Program Status Word (PSW) contain?

• Condition flags (zero, negative, carry, overflow)

• Interrupt enable bit

• Processor mode/privilege level (user vs supervisor)

Why must PSW be saved on interrupt entry?

• ISR executes its own ALU operations and updates flags

• Destroying interrupted program's state

• Restoring PSW restores flags, mode, and interrupt-enable state in one atomic step

What is the Interrupt Vector Table (IVT)?

• Table in memory mapping each interrupt source to handler address

• Stored at known, fixed location so hardware can find it

• Interrupt number used as index into IVT%

• Usually contains reset vector and CPU exception entries

What are the two things hardware saves automatically on interrupt?

• Program Counter (PC) - knows where to return

• Program Status Word (PSW) - preserves flags and mode

What does the software (ISR start) do on interrupt entry?

• Disables further interrupts (prevents nesting by default)

• Saves additional state (general-purpose registers ISR will clobber)

• May re-enable interrupts if nested interrupts wanted and safe

What does the Return from Interrupt (RETI) instruction do?

• Restores PSW and PC atomically

• Resumes interrupted program exactly where left off

• Restoring PSW re-enables interrupts (since enabled in saved PSW)

What are the three rules for keeping ISRs fast?

• Avoid loops

• Avoid heavy instructions (like printf)

• Avoid blocking instructions (like scanf)

Why is printf heavy in an ISR?

• Printf is a mini-interpreter (parses format string at runtime)

• Requires huge chunk of C library (especially with float formatting)

• Execution time unbounded and data-dependent (longer strings take longer)

Why is printf non-reentrant?

• Variadic format parser tracks position in format string

• Output buffering uses shared buffers

• newlib's stdio routes state through single _impure_ptr

What is reentrant code?

• Function safely called again before previous call finished

• Uses only stack-based local variables, parameters, and return values

• Avoids static variables, globals, or shared buffers

What are the benefits of disabling interrupts for whole ISR?

• No need for reentrant code (ISR cannot be re-entered)

• Stack depth bounded (no nested ISRs piling state)

• Easier reasoning (races between ISRs cannot occur)

What are the downsides of disabling interrupts for whole ISR?

• Increases latency for other interrupts arriving during ISR

• Can lead to lost interrupts (if same source fires again)

• 20ms ISR every 100ms means main loop loses 20% CPU

What is interrupt latency?

• Time between interrupt arriving and CPU starting ISR

• Deterministic latency: always the same (system can adapt)

• Variable latency called jitter

What are the four contributors to interrupt latency?

• Current instruction must complete

• Critical sections (cli…sei) block all interrupts

• Saving state (PC, PSW, registers) onto stack

• Fetching and jumping through vector table

Which latency components contribute to jitter?

• Instruction-completion delay (depends which instruction and where in cycle)

• Critical sections (depends if interrupts disabled and for how long)

• Hardware/software state save does NOT contribute (fixed cost)

What is jitter?

• Variability in latency between firings of same interrupt

• Difference between worst-case and best-case latency

• High jitter forces conservative design margins (must assume worst case)

What is the Global Flag Pattern for ISRs?

• Split response into two parts

• ISR (top half): grabs time-critical data, signals work pending

• Main loop (bottom half): does heavy lifting (parsing, checksums, decisions)

What are the four steps of the Global Flag Pattern?

1. Move data to buffer (read from peripheral register)

2. Set global flag (volatile uint8_t, atomic on most architectures)

3. Return immediately from ISR

4. Main loop checks flag and does heavy work

Why is volatile essential for the global flag?

• Main loop sits in while(!flag) only changed by ISR

• Without volatile, compiler caches flag in register (never re-reads memory)

• volatile forces read from memory on every access

When copying a volatile variable to local in ISR, when is it safe?

• Safe only if ISR keeps interrupts disabled

• Otherwise original could change underneath you

• Lets compiler optimise inner ISR code while keeping main-loop accesses safe

What are the three components of event-driven program structure?

• Initialization (configure peripherals, enable interrupts)

• Main loop (typically empty while(1) or sleep instruction)

• ISRs (one per event source, handle events as they arrive)

Why is empty/sleeping main loop a feature?

• If nothing happening, CPU has nothing to do

• Sleeping saves power (CPU wakes only on interrupt)

• Critical for battery-powered devices (car key fob lasts years)

What is a Moore machine?

• Output depends only on current state

• Not on which transition was taken to reach it

• Standard model used in embedded systems

What is a Mealy machine?

• Output depends on state AND input

• More powerful but harder to reason about

• Contrast with Moore machine

What are internal events?

• Originate from inside the chip

• Examples: timer overflow, ADC conversion complete, watchdog timeouts

• Same mechanism as external events (interrupt fires, ISR runs)

What are external events?

• Originate from outside world

• Examples: analogue comparator exceeds threshold, keyboard input, display refresh cycle

• Same mechanism as internal events (interrupt fires, ISR runs)

What six questions must be analysed for each event source?

1. Maximum arrival rate (can events be lost?)

2. Deadline for servicing (when must response complete?)

3. Cost if deadline missed (benign, expensive, or catastrophic?)

4. What part of response is time-sensitive?

5. Longest time interrupts are disabled?

6. Impact on other real-time code?

Where does the Interrupt Vector Table (IVT) live and why?

• At start of program memory (lowest addresses of flash)

• Must be at known, fixed location (hardware can't be told where)

• Lives in flash on Harvard architectures (must survive power-off)

What is the Reset Vector?

• Vector at address $0000

• Entry point on power-up (PC initialised to $0000)

• Same mechanism handles timer overflow and "system just started"

What are the three things that must be true for interrupt to fire?

1. ISR written and placed in correct vector slot

2. Interrupt enabled at device level (peripheral control register)

3. Interrupts globally enabled (sei() sets I-bit in status register)

What is conventional interrupt initialisation order?

• Configure peripherals while interrupts globally disabled

• Enable individual peripheral interrupts

• Enable interrupts globally as last step before main loop

What happens if you enable interrupt with no ISR?

• Vector slot may contain garbage (PC jumps to arbitrary address)

• Modern compilers fill unused slots with reset address (system resets repeatedly)

• Looks like dead device from outside (constant resetting prevents normal initialisation)

What is the payoff of using indirection table (IVT) rather than hard-coded jumps?

• Can swap out entire interrupt-handling behaviour in one operation

• One pointer write reconfigures entire interrupt system

• Use cases: bootloaders, emergency modes, different phases of program

What is DMA (Direct Memory Access)?

• Hardware controller moves bytes between peripheral and RAM without CPU

• CPU interrupted only when entire transfer completes

• For high-throughput data (audio, ADC streaming) where even efficient ISR consumes too many cycles